The present invention relates to a clock distribution system in an integrated circuit and, more particularly, for a clock distribution system that selectively disables selective units in an integrated circuit.
The increased processing power of modern integrated circuits has caused a corresponding increase in the power consumption of those circuits. Increased power consumption can lead to a variety of disadvantageous properties including generation of heat that may damage the integrated circuit, decreased battery life for portable devices and higher overall operating expense for computer systems. With all of these disadvantages, there is an increasing interest in the development of integrated circuits that provide increased processing power while, at the same time, decreased power consumption.
Power management techniques are commonplace in the modern computer. Users of domestic personal computers will recognize that computer monitors, disk drives and the like often are disabled when not in use. However, such techniques are not able to keep pace with the ever-increasing power demands made by newer generations of integrated circuits. Accordingly, there remains a need in the art for an integrated circuit architecture that contributes to reduced power consumption of the integrated circuit.
Embodiments of the present invention provide a hierarchical power control system for an integrated circuit. The power control system may be integrated in a clocking system that includes a global clock generator, a clock distribution network in communication with the global clock generator and a plurality of functional unit blocks each in communication with the global clock generator. The hierarchical power control system may include a first power controller provided in a communication path between the global clock generator and the clock distribution network, and a plurality of second power controllers, one provided in each communication path between the clock distribution network and a functional unit block.